Computing system memory architectures may be structured as various levels of host processor-side caches (e.g., level one/L1 cache, level 2/L2 cache, last level cache/LLC) and a system memory that includes a memory-side cache (e.g., “near memory”) and additional memory (e.g., “far memory”) that is slower to access than the memory-side cache.
When a search for data in the near memory is unsuccessful (e.g., a memory-side cache miss occurs), the requested data may be retrieved from the far memory. Frequent misses in the near memory may reduce performance and increase power consumption due to the retrieval of data from the relatively slow far memory. While hit-miss prediction techniques may exist for relatively small host processor-side caches, such techniques may not be scalable to larger memory-side caches in terms of accuracy or predictor size/overhead.